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RF3334
0
RoHS Compliant & Pb-Free Product Typical Applications * Cable Set Top Box * General Purpose Downconverter * Commercial and Consumer Systems
IF LOW NOISE AMPLIFIER/MIXER
Product Description
The RF3334 is an IF LNA/Mixer suitable for downconversion of forward channel control data in a set-top box application. It consists of a single-ended 75 terminated LNA, followed by a differential gain control stage with 30dB of analog gain control and a double-balanced mixer. The mixer load is available via pins 10 and 11 should an external filter be required. The mixer output is connected to an IF amplifier that can be configured from 10dB to 40dB gain with an external resistor. The amplifier is capable of 6V pk-pk output into a 1k load.
-A-
2 PLCS 0.10 C A
0.05 C
4.00 SQ. 2.00 TYP
0.10 C B 2 PLCS
0.70 0.65
0.90 0.85 0.05 0.00
12 MAX
0.10 C B 2 PLCS -B-C-
1.87 TYP 3.75 SQ
0.10 C A 2 PLCS
SEATING PLANE
Shaded lead is pin 1.
Dimensions in mm.
0.10 M C A B
0.60 0.24
TYP
0.35 0.23
Pin 1 ID 0.20 R
2.25 SQ. 1.95 0.75 TYP 0.50 0.65
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
Package Style: QFN, 16-Pin, 4x4
Features * 30dB RF Gain Control * 40dB IF Gain Control
RFVCC
GND
LOB
* 5dB Max. Noise Figure SSB * LNA Input Internally Matched to 75
12 RFAGC
16 RFDEC 1
15
14
13
LO
* Single 5V Supply
RFIN 2
11 MIXLOAD
GND 3
IF AMP
10 MIXLOADB
Ordering Information
9 GND 6 7 IFOUT 8 IFOUTB RF3334 LNA Mixer RF3334PCBA-41X Fully Assembled Evaluation Board
IFVCC 4 5 IFSET
IFSETB
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A6 061016
8-457
RF3334
Absolute Maximum Ratings Parameter
Supply Voltage IF Input Level Operating Ambient Temperature Storage Temperature
Rating
-0.5 to 7.0 500 -40 to +85 -40 to +150
Unit
VDC mVpp C C
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
DC Specifications
Supply Voltage Supply Current RFAGC Control Voltage RFAGC Input Impedance
Specification Min. Typ. Max.
4.75 20 0.5 5 24 5.25 4.5 300
Unit
V mA V k
Condition
0.5V=Minimum Gain 4.5V=Maximum Gain
AC Specifications
LNA+AGC+Mixer
RF Frequency Range 0 to 700 MHz On-chip signal path is DC-coupled, minimum frequency depends on external AC coupling components. On-chip signal path is DC-coupled, minimum frequency depends on external AC coupling components. At 100MHz Defined by on-chip first-order low-pass filter Differential At 100MHz RFAGC=4.5V RFAGC=0.5V Maximum Gain LNA Input to Mixer Output LNA Input to Mixer Output SSB, Cascaded LNA, AGC & Mixer
RF Input 3dB Bandwidth
700
MHz MHz dB dB dBV(rms) dBV(rms) dBV(rms) dB MHz dBuV MHz dB dB
RF Input Impedance RF Input VSWR Mixer Output 3dB Bandwidth Mixer Output Impedance Mixer Output VSWR Maximum Gain Minimum Gain Output 1dB Compression Input IP3, Maximum Gain Input IP3, Minimum Gain Noise Figure
27
75 1.4 100 300 1.2 30 -2 90 78 79 5 0 to 800 75 1.6:1
LO
LO Frequency Range LO Input Impedance LO Input VSWR LO Input Level LO Bandwidth LO Rejection to RF Input LO Rejection to Input of IF Amplifier Differential
80 800 50 65
IF Amplifier
IF Frequency Range Input Impedance Output Impedance Differential Voltage Gain Gain Set Resistor=2500 Gain Set Resistor=140 Gain Set Resistor=5 IF 3dB Bandwidth Equivalent Input Noise Output Swing Output 1dB Compression Output IP3 0 to 120 4000 10 10 31 40 140 1.5 6 127 137 8 MHz dB dB dB MHz Vrms VP-P dBV(rms) dBV(rms) Differential Differential R1=1k R1=1k R1=1k Gain Set=5 Gain Set=140 Into 1k load, at 50MHz Into 1k load, at 50MHz Into 1k load, at 50MHz
8-458
Rev A6 061016
RF3334
Parameter
Thermal
ThetaJC Maximum Measured Junction Temperature at DC Bias Conditions 65 95 C/W C
Specification Min. Typ. Max.
Unit
Condition
VCC =5.25V, VRFAGC=4.5V, ICC =29mA, PDISS =154mW TAMB =+85C
Rev A6 061016
8-459
RF3334
Pin 1 Function RFDEC Description
External decoupling capacitor for RF single-ended to differential converter.
Interface Schematic
VCC
100 RFDEC
2
RF
LNA Input, Internally matched to 75. Should be AC-coupled.
VBIAS RF
3 4 5
GND IFVCC IFSET
Ground. 5V supply for IF section. IF Gain select. The resistance between this pin and pin 6 (IFSETB) determines the gain of the IF amplifier. Maximum gain is achieved by placing a short circuit between the pins. Larger values of resistance will reduce the IF gain according to the following equation where R is the value of resistance between pins 5 and 6. IFGain=20log(1600/(R=75))15. Complementary IF Gain select.
IFSET
IFSETB
6
IFSETB
IFSET
IFSETB
7
IFOUT
IF Amplifier Output. Differential output of the IF amplifier. The differential load across this pin and pin 8 (IFOUTB) should be 1k or greater for optimal performance. The differential output impedance across this pin and pin 8 in 10.
VBIAS
VCC
IF OUT
8
IFOUTB
Complementary IF Amplifier Output.
VCC
VBIAS
IF OUTB
9 10
GND MIXLOADB
Ground. Complementary Mixer load.
MIXLOAD MIXLOADB
11
MIXLOAD
Differential output of the RF mixer. A resonant load should be applied to this pin and pin 10 (MIXLOADB) that will act as a bandpass filter at the desired IF frequency. VCC should be supplied to this pin via an inductor or a resistor. Use of a resistor will degrade intermodulation performance.
MIXLOAD MIXLOADB
8-460
Rev A6 061016
RF3334
Pin 12 Function RFAGC Description
RF Gain select voltage input. The voltage applied to this pin sets the gain of the RF amplifier. The voltage applied to this pin should be between 0.5V and 4.5V. The RF gain characteristic is such that 0.5V yields a gain of -2dB and 4.5V yields a gain of +30dB as measured from the input of the LNA to the output of the mixer stage. Differential LO Input. This pin and pin 14 (LOB) are the differential LO inputs. This input should be AC-coupled. The differential input impedance across pins 13 and 14 is 75. The LO may be driven single ended but will require a higher drive level. If a single ended LO is applied, pin 14 should be AC-coupled to ground.
Interface Schematic
100 k RFAGC 10 k VREF
13
LO
LOB 300 VBIAS 300 LO 75
14
LOB
Complementary LO Input. Should be AC-coupled.
LOB 300 VBIAS 300 LO 75
15 16 GND
GND RFVCC Paddle
Ground. 5V supply for RF section. Backside of package should be connected to ground.
Rev A6 061016
8-461
RF3334
Pin-Out
RFVCC
GND
LOB
16 RFDEC 1
15
14
13 12 RFAGC
LO 11 MIXLOAD 10 MIXLOADB 9 GND 8 IFOUTB
RFIN 2
GND 3
IFVCC 4 5 IFSET 6 IFSETB 7 IFOUT
8-462
Rev A6 061016
RF3334
Application Schematic
LOB LO
VCC
10 nF
10 nF
1 k RFAGC 10 nF
+
1 uF
1 nF
10 pF 16 15 14 13 12
C
10 nF 1 L RFIN 10 nF 3 VCC 4 10 n 5 6 7 8
IF AMP
2
11 R L 10 C VCC
9
IFOUT IFOUTB R*
Rev A6 061016
8-463
RF3334
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
T1
50 strip
J2 LO
TTWB-1-A
R1 1 k RFAGC C4 10 nF
VCC + C1 1 uF C10 1 nF C2 10 nF 1 J3 RF IN 50 strip 2 C3 10 nF 3
IF AMP
C11 10 pF 16 15 14 13 12
C5 82 pF
L1 120 nH R6 750 L2 120 nH C8 82 pF
11
VCC
10
VCC C6 10 nF J1 J1-1 1 2 J1-3 3 CON3 VCC GND RF AGC
4 5 6 7 8
9
R3 475 R2 140 R4 475 R5 100
C7 10 n C9 10 n
J4 IFOUT J5 IFOUTB
8-464
Rev A6 061016
RF3334
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.032", Board Material FR-4, Multi-layer
Rev A6 061016
8-465
RF3334
RF Input, Temp = +25C
1.0
0.6
Swp Max 0.2GHz
LO Input, Temp = +25C
1.0
0.6
Swp Max 0.2GHz
2.0
0.8
2. 0
3.0
0.2
0.8
0. 4
10.0
10.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0 4.0 5.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0 5.0
0
0
.4 -0
-0
.4
.0 -2
-0.
-0.8
Swp Min 0.05GHz
-0.
.0 -2
6
6
Swp Min 0.05GHz
-1.0
-0.8
8-466
-1.0
Rev A6 061016
-4. 0 -5.0
-3 .0
-4 . 0 -5.0
-0.2
0
-0.2
-10.0
-10.0
-3 .
0.
4
0 3.
4.0 5.0
4.0 5. 0
0.2
10.0
10.0
RF3334
35.0
LNA + AGC + Mixer Gain versus Control Voltage over Temperature (Freq = 100 MHz, VCC = 5.0 V)
90.0 88.0 86.0
LNA + AGC + Mixer + IF AMP - IIP3 versus Gain over Temperature (Freq = 100 MHz, VCC = 5.0 V)
30.0
25.0 84.0
15.0
IIP3 (dBV)
20.0
Gain (dB)
82.0 80.0 78.0 76.0
10.0
5.0 -40C 0.0 +25C +85C -5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 70.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 74.0 72.0 -40C +25C +85C
RFAGC (V)
Gain (dB)
35.0
SSB, Cascaded Noise Figure versus Gain over Temperature (Freq = 100 MHz, VCC = 5.0 V)
-40C +25C
RF Input VSWR versus Frequency Across Temperature
1.40 1.38 1.36 1.34
(VCC = 5.0 V)
30.0
+85C
25.0
Noise Figure (dB)
RF Input VSWR
20.0
1.32 1.30 1.28 1.26 1.24 -40C +25C +85C
15.0
10.0
5.0 1.22 0.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 1.20 70.00 80.00 90.00 100.00 110.00 120.00
130.00
Gain (dB)
Frequency (MHz)
1.75
LO Input VSWR versus Temperature Across Temperature (VCC = 5.0 V)
1.70
LO Input VSWR
1.65
1.60
1.55
-40C +25C +85C
1.50 118.00 128.00 138.00 148.00 158.00 168.00 178.00
Frequency (MHz)
Rev A6 061016
8-467
RF3334
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.69 x 0.28 (mm) Typ. B = 0.28 x 0.69 (mm) Typ. C = 2.40 (mm) Sq.
Dimensions in mm.
1.95 Typ. 0.65 Typ.
Pin 16 B Pin 1 A A A C A A A A B B B B Pin 8 B B B Pin 12
0.65 Typ.
A
0.98 1.95 Typ.
0.81 Typ.
0.81 Typ. 0.98
Figure 1. PCB Metal Land Pattern (Top View)
8-468
Rev A6 061016
RF3334
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.79 x 0.38 (mm) Typ. B = 0.38 x 0.79 (mm) Typ. C = 2.50 (mm) Sq.
Dimensions in mm.
1.95 Typ. 0.65 Typ.
Pin 16 B Pin 1 A A A C A A A A B B B B Pin 8 B B B Pin 12
0.65 Typ.
A
0.98 1.95 Typ.
0.81 Typ.
0.81 Typ. 0.98
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Rev A6 061016
8-469
RF3334
8-470
Rev A6 061016

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